An electronic circuit includes in many cases devices having various functions so as to communicate digital information items between these devices. The digital information is usually transferred through a bus.
For example, in a case where a central processing unit (CPU) reads data from a memory or writes data in a memory by use of a data bus, if the CPU is operated at a high speed, the data setup time margin is reduced. In order to overcome this difficulty, it is necessary to stabilize and establish a signal on the data bus to a predetermined state as quickly as possible.
Particularly, when compared with the data write operation of the CPU into a memory, the data read operation from a memory requires the signal to be more quickly stabilized on the data bus. The reason therefor will be described with reference to FIGS. 25 and 26. FIG. 25 is a timing chart of signals employed when the CPU writes data in a memory system. In the figure, CLK denotes a clock signal. When a CPU write cycle is initiated, the CPU supplies an address (Address OUT) and data (DATA OUT) onto the bus.
Based on the address signal, a memory chip select signal CS (low active) and a memory write enable signal WE (low active) are produced so as to be delivered to the memory system. When the signals CS and WE are set to be active, the data on the bus is written in the memory system. When the CPU writes data in the memory system, a setup time of write data is determined with reference to a rising edge of the WE signal. In the timing chart of FIG. 25, Rtsu designates a period of time to be elapsed from when the data is inputted to the memory to when the WE signal rises.
FIG. 26 shows a timing chart of signals used when the CPU reads data from the memory system. In the figure, CLK indicates a clock signal.
When a CPU read cycle is started, the CPU outputs an address (Address OUT). Based on the address, a CS signal (low active) is produced so as to be inputted to the memory system. After the CS signal becomes active and when a memory access time Wtoe is elapsed, data (DATA OUT) is delivered from the memory. Thereafter, when an output enable signal OE (low active) is set to be active, the data sent from the memory is supplied onto the data bus s as to be inputted to the CPU (DATA IN).
In the CPU read cycle, the falling edge of the last CLK of the cycle is assumed as a reference of data setup time. In the chart of FIG. 26, Wtsu denotes a period of time from when the data is inputted to the CPU to when the clock signal CLK falls.
As can be seen from Rtsu of FIG. 25 and Wtsu of FIG. 26, there exists a relationship Rtsu&gt;Wtsu. In consequence, when the operation speed of the CPU is increased, the CPU read operation first fails, before the CPU write operation, because a necessary data setup time cannot be obtained, which leads to a CPU read error. Moreover, due to occurrences of problems such as a signal reflection on the data bus, the period of Wtsu is further reduced when a period of time in which the data is stabilized on the data bus is taken into consideration. Namely, it is quite difficult to satisfy the condition of the data setup time necessary for the operation.
For the reasons above, in the memory read operation of the CPU, the signal on the data bus is required to be stabilized at a higher speed as compared with a case of the memory write operation of the CPU.
In the description above, it is assumed that a period of time from the falling edge of the CLK to the falling edge thereof is set as one cycle and the CS, WE, and OE signals are low active signals. However, the similar description applies to a case where a period from the rising edge of the CLK to the rising edge thereof is set as one cycle and at least one of the CS, WE, and OE signals is a high active signal.
As described above, in a system comprising, for example, a CPU and a memory, when the CPU is operated at a high speed, it is necessary to stabilize the signal on the data bus to establish data as quickly as possible. This is particularly highly required when the CPU reads data from the memory.
Next, a description will be given, with reference to an example of a case where the CPU reads data from the memory system by use of a data bus, of a conventional method of quickly stabilizing the signal on the bus when the CPU operates at a high-speed and the bus is driven at a high speed.
In the configuration of FIG. 27, a CPU system 126 is connected to a memory system 127 through an address and control bus 129 and a data bus 128. The data bus 128 is linked with resistors R.sub.1 130 and R.sub.2 131. Each resistor R.sub.1 130 has another end connected to a potential Vcc, whereas each resistor R.sub.2 131 has another end linked with a potential GND. In this system, if the resistors R.sub.1 130 and R.sub.2 131 are not provided, for a CPU read operation, the CPU system 126 has a high input impedance and the data bus line develops a low characteristic impedance of about 30 to 60 ohm; consequently, there appears a large impedance difference. In consequence, a signal reflection takes place at a connecting point between the CPU and the data bus, namely, at a termination point of the data bus, which prevents the signal from being easily stabilized on the data bus line. Conventionally, in order to cope with this disadvantageous situation, the resistors R.sub.1 130 and R.sub.2 131 are provided to lower the impedance at the terminal end of the data bus line to establish an impedance matching thereat. In this specification, these resistors are called terminal processing resistors. In this connection, for the technology of this kind, reference may be made, for example, to pages 451 to 452 of the "Transistor Gijutsu" (Transistor Technology), May, 1985, (CQ Inc.) Furthermore, as a method of representing the terminal processing resistors, there will be employed herebelow a representation method in which the configuration of FIG. 27 is represented as shown in FIG. 28.
However, for example, if a TTL buffer is used as a drive of a signal to be outputted to the data bus, since the bus drive capacity of the buffer has an upper limit, it is impossible to unconditionally reduce the values of resistors R.sub.1 and R.sub.2. Namely, these values R.sub.1 and R.sub.2 are restricted by lower limits. For example, if a usual TTL buffer is adopted as the bus driver, the terminal impedance of the bus line cannot be easily set to be equal to or less than 200 ohm. The impedance is still greatly different from the characteristic impedance 30 to 60 ohm of the data bus line. In consequence, the influence of the reflection cannot be completely removed, which prevents the signal to be quickly stabilized on the bus.
On the other hand, in a case where a driver having a greater drive capacity than the TTL buffer is employed, such a driver is expensive and hence the system cost soars. Moreover, the heat dissipation in the driver and the termination processing resistors is increased, which unfavorably necessitates a large power consumption.